Computer storage systems (such as optical, magnetic, and the like) record digital data onto the surface of a storage medium, which is typically in the form of a rotating magnetic or optical disk, by altering a surface characteristic of the disk. The digital data serves to modulate the operation of a write transducer (write head) which records binary sequences onto the disc in radially concentric or spiral tracks. In magnetic recording systems, for example, the digital data modulates the current in a write coil in order to record a series of magnetic flux transitions onto the surface of a magnetizable disk. And in optical recording systems, the digital data may modulate the intensity of a laser beam in order to record a series of "pits" onto the surface of an optical disk. When reading this recorded data, a read transducer (read head) positioned in close proximity to the rotating disc detects the alterations on the medium and generates a sequence of corresponding pulses in an analog read signal. These pulses are then detected and decoded by read channel circuitry in order to reproduce the digital sequence.
Detecting and decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete-time sequence detector in a sampled amplitude read channel. Discrete-time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. Consequently, discrete-time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete-time sequence detection methods including discrete-time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete-time instances, the actual value of the pulse data. To this end, the read channel comprises a sampling device for sampling the analog read signal, and a timing recovery circuit for synchronizing the samples to the baud rate (code bit rate). Before sampling the pulses, a variable gain amplifier adjusts the read signal's amplitude to a nominal value, and a low pass analog filter filters the read signal to attenuate channel and aliasing noise. After sampling, a discrete-time equalizer equalizes the sample values according to a desired partial response, and a discrete-time sequence detector, such as a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the digital data (i.e., maximum likelihood sequence detection (MLSD)). MLSD takes into account the effect of ISI and channel noise in the detection algorithm, thereby decreasing the probability of a detection error. This increases the effective signal to noise ratio and, for a given RLL (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, "Partial Response Signaling", IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, September 1975; and Edward A. Lee and David G. Messerschmitt, "Digital Communication", Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278, March 1973.
Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, "Implementation of PRML in a Rigid Disc Drive", IEEE Trans. on Magnetics, Vol. 27, No. 6, Nov. 1991; and Carley et al, "Adaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detection", Digest of The Magnetic Recording Conference, Aug. 15-17, 1994, pp. C3; and Moon et al, "Constrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedback", IEEE Trans. on Magnetics, Vol. 30, No. 5, September 1994; and Abbott et al, "Timing Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channel", Globecom'90 IEEE Global Telecommunications Conference 1990, San Diego, Calif., November 1990, pp.1794-1799; and Abbott et al, "Performance of Digital Magnetic Recording with Equalization and Offtrack Interference", IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffi et al, "Adaptive Equalization in Magnetic-Disc Storage Channels", IEEE Communication Magazine, February 1990; and Roger Wood, "Enhanced Decision Feedback Equalization", Intermag'90.
The timing recovery circuit for synchronizing the read signal samples to the baud rate is a decision-directed phase-locked-loop (PLL). It computes a phase error between the read signal samples and the ideal or target partial response samples which is used to adjust the PLL until the read signal samples are synchronized. Conventionally, the phase error adjusts the output of variable frequency oscillator (VFO). The output of the VFO is a sampling clock for controlling an analog-to-digital converter (ADC) which samples the read signal synchronous to the baud rate. Alternatively, the read signal can be sampled asynchronously and the asynchronous sample values interpolated to generate the baud rate synchronous sample values. For details concerning this method of timing recovery, see the above referenced U.S. patent entitled "Sampled Amplitude Read Channel Employing Interpolated Timing Recovery."
The phase error is computed the same for both synchronous sampling and interpolated timing recovery. Conventionally, the target sample values for computing the phase error are generated by a slicer circuit. The slicer circuit generates an estimated target sample value by selecting the target sample closest to the current read signal sample. This can be implemented simply by comparing the read signal sample to a number of thresholds which correspond to the possible target samples of the partial response signaling space. For example, in the partial response class-IV signaling space, the target samples are +1, 0 and -1. Therefore, the slicer is implemented using a positive and negative threshold: if the read signal sample value is above the positive threshold the slicer outputs a +1, if the read signal sample value is below the negative threshold the slicer outputs a -1, otherwise the slicer outputs a 0. The advantage of using a simple slicer circuit to generate the estimated target sample value is its inherent low latency, particularly when acquiring the acquisition preamble (described below) where the loop bandwidth is set as high as possible in order to minimize the time (and bits) needed to acquire the preamble.
Similar to the timing recovery circuit, the gain control circuit for adjusting the gain of the read signal at the output of the VGA is also a decision-directed feed back system. A gain error is computed from the equalized sample values and estimated target sample values. The gain error is converted into an analog control signal which controls the gain of the VGA. Again, the latency of the gain loop impacts the overall performance of the read channel, therefore conventional read channels employ a slicer circuit for generating the estimated target samples for use in computing the gain error.
The discrete-time equalizer filter for equalizing the read signal sample values according to the desired partial response may be adaptively adjusted in real-time using a decision-directed feed back system. Similar to timing recovery and gain control, an adaptive equalizer computes an error value from the equalized sample values and estimated target sample values; the error value is then used to update the filter's coefficients. For example, the coefficients may be updated according to the well known least mean square (LMS) algorithm: EQU W.sub.k+1 =W.sub.k -.mu..multidot.e.sub.k.multidot.X.sub.k,
where W.sub.k represents a vector of filter coefficients, .mu. is a programmable gain, e.sub.k represents a sample error between the filter's actual output and a desired output, and X.sub.k represents a vector of sample values from the filter input. In other words, the LMS adaptive equalizer filter is a closed loop feedback system that attempts to minimize the mean squared error between an actual output of the filter and a desired output by continuously adjusting the filter's coefficients to achieve an optimum frequency response. The latency of this loop impacts the overall performance of the read channel; conventional read channels employ a slicer circuit to generate the estimated target samples in order to minimize this latency.
Another performance measurement of disc storage systems is the overall storage capacity which is continuously pushed higher by increasing the tracks per inch (TPI) and/or by increasing the linear bit density in the data sectors. However, when the linear bit density increases beyond a certain threshold, the accuracy of a simple slicer circuit degrades due to the increase in intersymbol interference. This degradation in the slicer error rate eventually has a significant adverse impact on the performance of gain control, timing recovery, and the adaptive equalizer-the decision-directed feedback loops are less effective if the decisions about the estimated targets samples are incorrect. This loss in performance propagates through to the discrete-time sequence detector, thereby increasing the bit error rate in the detected user data sequence. The increased number of bit errors can be corrected by employing more ECC redundancy symbols, but this is undesirable because it reduces the amount of recordable area for user data and it increases the cost and complexity of the ECC circuitry.
There is, therefore, a need for a more accurate technique to generate estimated target sample values for use in the decision-directed feed back loops of a sampled amplitude read channel. In particular, there is a need to generate accurate estimated target samples when the linear bit density increases to a level that renders a simple slicer circuit impracticable. Another object of the present invention is to avoid using estimated sample values altogether while acquiring the acquisition preamble, thereby obviating the latency problem inherent in prior art read channels.